Semiconductor devices are typically produced in arrays on wafer substrates ranging from 1 to 18 inches in diameter. The devices are then separated into individual devices or dies that are packaged to allow practical macro-level connection of the devices in the context of a larger circuit. As the requirements for chip density and smaller packaging form factors increase, advances have been made in three-dimensional integration of circuits. In this technology, devices are stacked, and bonded in the vertical or z-direction. Typically, the stacked devices are electrically coupled by electrical contact pads on the devices.
A popular process for vertically integrating devices is a wafer-to-wafer integration scheme in which the devices on one wafer are aligned with the devices on another wafer, and the wafers are bonded together using oxide-oxide fusion bonding. One of the wafers is then thinned to expose through silicon vias that connect to the other wafer, or is thinned followed by fabrication of through silicon vias that connect to the other wafer. One of the challenges for oxide-oxide fusion bonding is chipping, cracking, and delamination at the wafer edge zone during thinning of wafer stacks caused by bonding voids and defects. This is typically handled by performing an edge trimming step to remove the defective edge zone after bonding or after preliminary thinning, which results in reducing usable space on the wafer and reducing yield. If the final device comprises multiple layers, additional edge trimming after each wafer-to-wafer bonding and/or thinning may further reduce yield.
It would be desirable to have a bonding process that reduces or eliminates defects in the edge zone caused by bonding voids and defects, thus increasing the manufacturing yield.